題組內容

4. An enhancement NMOS transistor is connected in the bias circuit of Fig. 3 with V_G= 4 V and RS = 1 kΩ. The transistor has V_t = 2 V and k'n(W/L) = 2 mA/V².

(b) If a transistor for which k'n(W/L) is 50% higher is used, what is the resulting current “I_D”?
(10%)
　

題組內容

(b) If a transistor for which k'n(W/L) is 50% higher is used, what is the resulting current “I_D”?
(10%)

相關申論題

相關試卷

題組內容

(b) If a transistor for which k'n(W/L) is 50% higher is used, what is the resulting current “ID”?(10%)

相關申論題

相關試卷

(b) If a transistor for which k'n(W/L) is 50% higher is used, what is the resulting current “I_D”?
(10%)
　